SaE-FPGA: A Secure and Efficient DNN Accelerator on FPGA with Integrated Hash-Bypass and BRAM-LUT Mixed-Precision Booth Multiply

With the rapid deployment of deep neural networks (DNNs) on edge devices, traditional hardware accelerators face significant challenges in terms of data security, computational redundancy caused by sparsity, and uneven utilization of on-chip resources. This paper proposes SaE-FPGA, a secure and efficient DNN accelerator designed specifically for edge FPGA platforms. The architecture introduces three core innovations: (1) Hash-Bypass Processing Unit (HBPU): Integrating a high-speed SHA-256 hardware engine with a hash-sparse bitmap mechanism, it enables real-time data integrity verification within a single clock cycle while skipping computations for redundant zero-value data. (2) Flexible Mixed-Precision Processing Element (FMP): By reconfiguring idle BRAM and LUT resources into an active lookup table multiplication engine, it overcomes the physical bit-width limitations of DSP blocks and supports INT8/INT6/INT4 mixed-precision multiplication. (3) Multi-mode Reconfigurable Streaming Frame (MRSF): A sparse-aware, elastic load balancing and data routing mechanism designed to mask long memory access latencies and ensure high hardware resource utilization. Experimental results on the Zynq 7045 platform demonstrate that SaE-FPGA reduces redundant computations by 23.2% while maintaining high precision and minimizing precision loss. The system effectively mitigates the risk of physical tampering. When tested on ResNet-50, it achieved a 27.2% improvement in energy efficiency and a 2.97× speedup compared to DSP-based FPGA solutions. Furthermore, by fully exploiting the hybrid BRAM-LUT and DSP configuration, the proposed accelerator achieves a remarkable peak throughput of 782.4 GOPS.