Mechanical and Thermal Characterization of TSV Multi-chip Stacked Packages for Reliable 3D IC Applications

A multi-chip stacked package using through silicon-vias (TSVs) still has the reliability concerns due to tremendous number of TSVs and micro-bumps in the stacked chips. Cu-filled TSVs may bring about process-induced failures as copper protrusion or copper diffusion into silicon lattice. Micro-bumps have various failure modes such as non-wet, bump cracking, and head-in-pillow joints, which are obviously fatal in terms of long-term reliability of electronic products. At first, this paper introduces well-designed TSV test vehicles and test pattern architectures to address the robust and reliable 3D applications. Specially designed test features would provide the appropriate solutions how to ensure reliability as well as connectivity of TSVs and micro-bumps. This paper also describes several fault isolation techniques and physical failure analysis. And mechanical reliability of TSV multi-chip stack packages has been evaluated with proper test patterns. Finally thermal simulation and thermal resistance measurement results will be introduced for the understanding of thermal dissipation behavior.