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Conditional-sum addition is a new mechanism for parallel, high-speed addition of digitally-represented numbers. Its design is based on the computation of ``conditional'' sums and carries that result from the assumption of all the possible distributions of carries for various groups of columns. A rapid-sequence mode of operation provides an addition rate that is invariant with the lengths of the summands. Another advantage is the possibility of realizing the adder with ``integrated devices'' or ``modules.'' The logic of conditional-sum addition is applicable to all positive radices, as well as to multisummand operation. In a companion paper, a comparison of several adders shows that, within a set of stated assumptions, conditional-sum addition is superior in certain respects, including processing speed.
Jack Sklansky (1960) studied this question.