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May 31, 2026International Journal of Versatile Research and Analysis0 citationsOpen Access

Model-Based Design and Implementation of SDR MIMO-OFDM System onto an FPGA Using Near-maximum-likelihood Detection in FPGA-in-the-Loop Configuration

RMRehan Muzammil

Key Points

  • This research aims to develop a model-based design for a MIMO-OFDM system implemented on an FPGA, enhancing detection efficiency.
  • Developed a 4x4 MIMO-OFDM system with near-maximum-likelihood detection for real-time testing.
  • Utilized MATLAB/Simulink for modeling, and implemented the transceiver on the Xilinx Zynq UltraScale+ FPGA.
  • Generated HDL code for efficient hardware integration via MATLAB/Simulink.
  • Achieved effective detection performance with the FPGA implementation of the MIMO-OFDM system.
  • Demonstrated a significant reduction in design and testing time through model-based design techniques.
  • Real-time processing on FPGA validated the practical applicability of the design.

Abstract

The multiple-input multiple-output (MIMO) technology combined with orthogonal frequency division multiplexing (OFDM) is a dominant technology for 4G and 5G wireless communication systems. This paper studies a 4x4 MIMO with OFDM, and near-maximum-likelihood detection is used at the receiver. The 4-QAM multiplexing and demultiplexing are used at the transmitter and the receiver, respectively. IFFT and FFT systems perform the OFDM Modulation and Demodulation, respectively. The cyclic prefix is added to the transmitter using up-sampling and removed at the receiver using down-sampling. The transceiver is modelled in a MATLAB/Simulink environment and tested in real-time on an FPGA. The FPGA board used is the Xilinx Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit. This board has a System on a Chip (SoC) comprising an ARM processor and an FPGA. A part of the transceiver runs on the FPGA, and the rest runs on the ARM processor. The model-based design saves much time by combining design, coding, and testing. The MATLAB/Simulink HDL Workflow advisor generates the code automatically in C++ and VHDL.

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Cite This Study

Rehan Muzammil (2026) studied this question.

synapsesocial.com/papers/6a1bd0fa5783ba022b6fca58https://doi.org/10.56975/ijvra.v4i5.707208
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