Modern computing rests on a foundational, largely unexamined assumption: that information must persist. This paper challenges that assumption by proposing a single ordering relation as a foundational postulate for a contrary paradigm — the Temporal Decay Inequality: τcompute < τₛtate < τₐccess where τcompute is the time point at which result delivery to the downstream stage completes, τₛtate is the time point at which the electrical state of the compute node decays below the logic discrimination threshold, and τₐccess is the time point at which external observation of that state becomes circuit-topologically established. The architectural content of the inequality is an inversion: τₛtate — conventionally a lower-bound constraint sustained by refresh and keeper circuits — is here the primary, upper-bounded design variable, engineered short enough that the compute node's electrical state spontaneously decays below the logic discrimination threshold once its result has been forwarded, leaving no recoverable state behind. The postulate is grounded in three independent theoretical foundations: an information-theoretic argument (Shannon channel capacity available to an external observer decays to the noise floor before τₐccess), a thermodynamic argument (spontaneous decay obviates the active retention and active-erasure circuitry imposed by the persistence assumption, while still satisfying the Landauer floor through passive dissipation), and a circuit-realizability argument (two well-characterized mechanisms — capacitance-leakage discharge and thermodynamic barrier crossing — provide existence proofs). In the H100-class accelerator context the inequality is satisfiable with concrete numerical margin: τcompute ≤ 2 ns, τₛtate ≈ 5 ns at an illustrative 5 nm finFET design point, and τₐccess ≥ 20 ns from the HBM3 write path, yielding a left-inequality margin of 2. 5× and a right-inequality margin of 4–9×, established from published device and memory-subsystem specifications without novel physics or active runtime control. The inequality is an ordering relation among three time points, not a magnitude specification: as τₐccess varies across application environments and measurement technologies, τₛtate is designed accordingly, rendering the postulate robust against advances in physical measurement. Implications for energy dissipation, information non-lingering, and the structural relationship between state lifetime and memory-hierarchy requirements are derived.
JULGI KANG (2026) studied this question.