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June 13, 2017ACS Photonics171 citationsOpen Access

Silicon–Organic and Plasmonic–Organic Hybrid Photonics

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WHWolfgang HeniYKY. KutuvantavidaCHChristian Haffner

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Abstract

Chip-scale integration of electronics and photonics is recognized as important to the future of information technology, as is the exploitation of the best properties of electronics, photonics, and plasmonics to achieve this objective. However, significant challenges exist including matching the sizes of electronic and photonic circuits; achieving low-loss transition between electronics, photonics, and plasmonics; and developing and integrating new materials. This review focuses on a hybrid material approach illustrating the importance of both chemical and engineering concepts. Silicon–organic hybrid (SOH) and plasmonic–organic hybrid (POH) technologies have permitted dramatic improvements in electro-optic (EO) performance relevant to both digital and analog signal processing. For example, the voltage–length product of devices has been reduced to less than 40 Vμm, facilitating device footprints of <20 μm2 operating with digital voltage levels to frequencies above 170 GHz. Energy efficiency has been improved to around a femtojoule/bit. This improvement has been realized through exploitation of field enhancements permitted by new device architectures and through theory-guided improvements in organic electro-optic (OEO) materials. Multiscale theory efforts have permitted quantitative simulation of the dependence of OEO activity on chromophore structure and associated intermolecular interactions. This has led to new classes of OEO materials, including materials of reduced dimensionality and neat (pure) chromophore materials that can be electrically poled. Theoretical simulations have helped elucidate the observed dependence of device performance on nanoscopic waveguide dimensions, reflecting the importance of material interfaces. The demonstration and explanation of the dependence of in-device electro-optic activity, voltage–length product, and optical insertion loss on device architecture (e.g., slot width) suggest new paradigms for further dramatic improvement of performance.

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Heni et al. (2017) studied this question.

synapsesocial.com/papers/6a1fc5b9607d58129bdf600chttps://doi.org/10.1021/acsphotonics.7b00224
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