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June 17, 2019IEEE Transactions on Power Electronics184 citationsOpen Access

Symmetrical PLL for SISO Impedance Modeling and Enhanced Stability in Weak Grids

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DYDongsheng YangXWXiongfei WangFLFangcheng Liu

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Abstract

This paper proposes a symmetrical phase-locked loop (PLL) that can eliminate the frequency-coupling terms caused by the asymmetric dynamics of conventional PLLs. In the approach, a concept of complex phase angle vector with both real and imaginary phase components is introduced, which enables to control the direct- and quadrature-axis components with symmetrical dynamics. The small-signal impedance model that characterizes the dynamic effect of the symmetrical PLL on the current control loop is also derived, which, differing from the conventional multiple-input multiple-output impedance matrix, is in a single-input single-output (SISO) form based on complex transfer functions. This SISO representation allows for a design-oriented analysis. Moreover, the undesired sub-synchronous oscillation caused by the conventional asymmetrical PLL can be avoided, and the classical SISO impedance shaping can be utilized to cancel the negative resistor behavior caused by PLL; thus can greatly enhance the grid synchronization stability under weak grid conditions. The effectiveness of the theoretical analysis is validated by experimental tests.

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Cite This Study

Yang et al. (2019) studied this question.

synapsesocial.com/papers/6a2073e72079444d1ef5fae2https://doi.org/10.1109/tpel.2019.2917945
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