Synthesis of a CNTFET-Based Ternary Full Adder Using a Carry-Less Ternary Half Adder

The full adder (FA) is an essential element within arithmetic units, significantly contributing to their computational efficiency. Contemporary research endeavors are actively exploring optimized FA circuit designs. The integration of carbon nanotube field-effect transistors (CNTFETs) and multiple-valued logic (MVL) in circuit implementations holds great promise for achieving exceptional performance gains. This paper proposes novel complete and partial ternary FA (TFA) architectures utilizing 76 and 55 CNTFETs, respectively, realized through a streamlined design methodology. The design strategically incorporates a proposed carry-less ternary half adder to compute the sum of the primary inputs. The resulting Sum output then serves as a control signal in both TFA configurations. The TFA circuits are further implemented utilizing three unary operators, transmission gates, and pass transistor logic. HSPICE simulation results, conducted using Stanford 32-nm CNTFET technology at a VDD=0.9V, demonstrate that the proposed complete TFA design outperforms its counterparts with a 24.24% improvement in delay, a 5.81% reduction in power consumption, and a 28.71% decrease in energy consumption. Meanwhile, the proposed partial TFA offers 19.13% faster operation, 14.4% lower power consumption, and 30.74% better energy efficiency. The superiority of the proposed complete TFA is further substantiated through the creation of a three-trit ripple-carry adder.