ABSTRACT This paper presents a novel ultra‐low‐power CMOS reference voltage circuit incorporating segmented linear curvature compensation. In the proposed circuit, all MOS transistors are biased to operate in the subthreshold region via a dedicated subthreshold current source, enabling nanoampere‐level power consumption. The design is based on the BJT‐like exponential current characteristic of subthreshold MOS transistors, where the gate‐source voltage exhibits a complementary‐to‐absolute‐temperature dependence, thereby providing a CTAT voltage. A proportional‐to‐absolute‐temperature voltage is generated by subtracting the gate‐source voltages of two transistors biased at an identical drain current. A first‐order temperature‐compensated reference voltage is then obtained by the weighted summation of these CTAT and PTAT components. To further suppress the temperature coefficient, a novel segmented curvature compensation technique is introduced, in which a piecewise compensation current is synthesized from CTAT and PTAT currents, thereby significantly enhancing the thermal stability achieved from the first‐order compensation. The circuit is designed and simulated in the 180‐nm CMOS process. It occupies a core area of 0.007 mm 2 in layout. Simulated under 1.2‐V supply, it consumes 83.11 nW while providing a 0.2756‐V output. A temperature coefficient of 12.42 ppm/°C from −40°C to 125°C is achieved, and a power supply rejection ratio of −69.61 dB at 100 Hz is demonstrated. The combination of ultra‐low power consumption, low operating voltage, and high temperature stability renders the proposed reference particularly suitable for power‐management applications, such as low‐dropout regulators and energy‐aware sensor interfaces.
Liu et al. (2026) studied this question.