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Noise and signal integrity are important factors influencing the design process of microcircuits made using submicron technology. Currently, there is some difference in what design engineers can design and what can be manufactured with the right level of quality and reliability. Therefore, it is necessary to create a fundamentally new methodology for verifying VLSI projects with deep submicron design standards. In order to calculate the percentage of good chips manufactured, it is required to identify vulnerable effects and phenomena from the point of view of submicron technology. In this paper, the effect of noise on various types of microcircuits is studied and recommendations are given for limiting noise. One of the options for achieving the optimal balance between noise, noise immunity and microcircuit parameters is to add margins when calculating the VLSI parameters. The paper shows that VLSI projects with nanometer topological norms must undergo an additional process of verifying the parameters and functioning in general before issuing information for the production of photomasks. Verification requires the use of an integrated set of software tools that are certified in real production conditions.
Ачкасов et al. (2022) studied this question.