S. Narendra

Recent publications by S. Narendra

1. A Survey of Data Hiding TechniquesInternational Journal of Computer Applications · Thu,
2. Functional Yield Estimation of Carbon Nanotube-Based Logic Gates in the Presence of DefectsIEEE Transactions on Nanotechnology · Wed,
3. Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and AgingThu,
4. A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on packageIEEE Journal of Solid-State Circuits · Fri,
5. Challenges and design choices in nanoscale CMOSACM Journal on Emerging Technologies in Computing Systems · Tue,
6. Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS processIEEE Journal of Solid-State Circuits · Tue,
7. Low-Voltage-Swing Monolithic dc–dc ConversionIEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · Sat,
8. A TCP offload accelerator for 10 Gb/s ethernet in 90-nm CMOSIEEE Journal of Solid-State Circuits · Fri,
9. Dynamic sleep transistor and body bias for active leakage power control of microprocessorsIEEE Journal of Solid-State Circuits · Fri,
10. Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakageWed,