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August 31, 2004IEEE Journal of Solid-State Circuits

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process

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PHP. HazuchaTKTanay KarnikSWS.V. Walstra

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Hazucha et al. (2004) studied this question.

synapsesocial.com/papers/6aa92011d7d677827e255152https://doi.org/10.1109/jssc.2004.831449
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