This paper describes a controlled pre-silicon Design-for-Test (DFT) feedback loop mechanism that allows faster GPU productisation with less test cost. DFT is redefined in a one-time metallic achievement into an Observe → Analyze → Decide → Act → Verify loop nested within CI/CD. A typical telemetry model allows combining ATPG coverage, fault-simulation results, timing and power constraints, diagnosis artifacts, and provenance to perform auditable automation. The three levers that are the primary focus of controller policies are constraint tuning, timing-aware test-point insertion, and selective pattern regeneration, which have been verified for verification gains using A/B comparisons to frozen baselines under quality gates. Screening gains are observed on typical GPU partition types (streaming-multiprocessor cluster, L2 cache slice, and HBM PHY wrappers): +1.6 to 2.8 percentage-point stuck-at and +1.0 to 2.2 percentage-point transition coverage; 22 to 38 percent reduced patterns; tens of percent tester time savings; and fewer suspect sets in diagnosis. Orchestration capabilities: Content-addressed storage, checkpointed compute, license-aware scheduling, keep throughput and reproducibility, dashboards expose Pareto tradeoffs and undetected-fault heatmaps to concentrate the compute. The limitations include the cell-aware run time, high X-density, multi-clock interactions, analog adjacency, seed sensitivity, and inter-tool naming drift, which are all alleviated by incremental engines, cache reuse, schema normalization, ECO-safe edit windows, power-aware X-filling, and controlled rollbacks. Future research will focus on multi-objective controllers, LBIST/MBIST, and in-field telemetry, collection of fabrication/test-floor data, cross-generation transfer learning, and open benchmarks to achieve sustained comparability and reproducibility across GPU families at scale.
Karan Lulla (Mon,) studied this question.