Design and Analysis of Circular Sheet Junctionless Double Gate Vertical Nanotube (CSJL-DG-VNT) FET for DC/Analog/RF Applications: Device to Circuit Implementation

Abstract This paper investigates the influence of geometrical variations on the performance characteristics of a novel circular sheet junctionless double gate vertical nanotube (CSJL-DG-VNT) FET through 3D numerical simulations at sub-5nm technology node. Initially, the proposed device is compared with NWFET and NSFET, and shown favourable performance. The ION/IOFFcurrent ratio is improved to 51.9% when gate length (Lg) is sweeping from 8nm to 12nm. The decrease in Lg leads to enhanced analog/RF metrics such as gm, gm/Id, and fT. It was observed that opting for the shortest Lgmay be advantageous for certain parameters, albeit at the expense of others, depending on the specific application requirements. Further, while maintaining a constant Lg, variations in the thickness tNTfrom 5 to 10 nm were carried out to evaluate the analog/RF performance for device optimization. It was observed that lower tNT(5nm) values yielded improved IOFF current around ~ 2 order and DIBL is 32.77% when compared with higher tNT(10nm) due to ameliorated channel control from both inner and out gate of VNT. Subsequently, at an optimal Lg and tNTthe temperature (T) varied from 250 K to 450 K to analyze the device characteristics, indicating that a lower T should be favoured. Furthermore, the device is used for designing a common-source (CS) amplifier with tNTvariations and noticed that at 5nm of tNToutperforms highest gain (AV) ~ 6.8V/V when compared to 7nm and 10nm.