Efficient Hardware Architecture Design of Radix-22 Fast Fourier Transform Using Coordinate Rotation Digital Computer

The fast Fourier transform (FFT) is a widely used algorithm for computing the discrete Fourier transform (DFT) in real-time signal processing. Achieving high performance with minimal resource usage is crucial for any real-time application. This paper introduces an architecture based on coordinate rotation digital computer (CORDIC) for implementing a radix-Formula: see text FFT. Traditional FFT implementations require complex twiddle factor multiplications, which is not cost-effective in terms of hardware utilization. To address this issue, we have proposed a radix-8 CORDIC-based approach integrated with FFT computation. The proposed radix-8 CORDIC requires fewer stages than the conventional radix-2 CORDIC, enhancing computational efficiency and reducing hardware utilization. The feedforward radix-Formula: see text FFT architecture is presented where the butterflies of the FFT are computed with the help of radix-8 CORDIC. A total of three FFT architectures are developed supporting 16-, 1024- and 2048-point FFTs. The proposed FFT architectures are developed using Verilog-HDL code and implemented on a Virtex-7 field-programmable gate array (FPGA). The FPGA-based radix-Formula: see text FFT achieves a clock frequency of 323.4Formula: see textMHz and utilizes minimal FPGA resources. Processing of 2048 data samples takes only 4.06Formula: see textFormula: see textS by the proposed FPGA-based design. Additionally, two ASICs have been designed: the 1024-point FFT ASIC occupies an area of 1.079Formula: see textmm 2 , and the 2048-point FFT ASIC occupies an area of 1.544 mm 2 . The proposed FFT ASICs have better-normalized area per FFT and energy per FFT than the state-of-the-art designs.