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The demands of 5G, Internet of Things and other global technology trends, combined with the increasing cost of scaling down process nodes, have created a shift towards more integrated packaging requirements. The emergence of advanced packaging technologies, such as Fan-Out Wafer Level Packaging (FOWLP), 2.5D/3D IC packaging, and heterogenous integration, brings potential for smaller form factors with increased functionality and bandwidth 1. Backside processing or thinning of the device wafer is often needed for enabling these technologies. This requires the device wafer be adhered to a rigid carrier wafer using a temporary bonding material (TBM) for mechanical support during handling and processing. Following carrier release, the TBM must be thoroughly removed and cleaned from the device wafer. Many of these adhesives are exposed to high-power lasers or elevated temperatures, making removal more challenging. Sub-micron particle level clean demands for temporary bonding material (TBM) removal are also reaching standards typically reserved for front-end-of-line (FEOL) processing. This is especially crucial in 3D processes such as hybrid bonding where feature and pitch sizes are nearing <1 µm and insufficient cleaning can lead to failures in subsequent bonding processes 2. Thus, careful consideration of all processing steps is necessary to meet stringent particle demands. This work investigates the removal of coated and baked TBM on silicon wafers, with an emphasis on processing conditions that obtain best particle results. Several chemistries were assessed at the beaker level by performing coupon-level studies and measuring surface properties. Based on these findings, studies with 300-mm wafers were performed using a customizable single-wafer processing tool.
Bahena et al. (Thu,) studied this question.