Improvement of Extended‐Source TFET With Dopant‐Segregated Schottky‐Barrier Drain for Ambipolar Performance

This article presents an extended‐source double‐gate dopant‐segregated Schottky‐barrier drain tunneling field‐effect transistor (ES DG DSSBD TFET) designed to enhance the ON‐state current ( I ON ) while simultaneously decreasing OFF‐state leakage ( I OFF ) and ambipolarity. The extended‐source increases tunneling area, enhancing I ON and subthreshold swing (SS); the dopant‐segregated Schottky barrier minimizes carrier tunneling during ambipolar conditions, significantly reducing both I OFF and ambipolar current ( I AMB ). Comparative analysis is conducted with two additional TFET configurations based on the extended‐source structure: ES DG Silicon‐drain TFET (Device D‐1) and ES DG Schottky‐barrier‐drain TFET (Device D‐2). 2D TCAD simulations at V DS = 1 V and V GS = −1 V show that the I AMB for the proposed device reaches a remarkably low value of 2.62 × 10 −16 A/μm, representing reductions by factors of approximately 9.78 × 10 7 and 3.89 × 10 5 when compared to Device D‐1 (2.56 × 10 −8 A/μm) and Device D‐2 (1.02 × 10 −10 A/μm), respectively. Furthermore, the I ON / I OFF ratio for the investigated device achieves 4.69 × 10 13 , while the average subthreshold swing (SS avg ) is recorded at 29.2 mV/dec. Key design parameters are explored, and reliability is evaluated through the effects of interface trap charges (ITCs) and hot‐carrier stress (HCS).