Dynamic Power‐Aware Routing and Flow Management for Scalable 3D Wireless Network‐on‐Chip Communication Systems

ABSTRACT The purpose of this research is to develop an efficient and scalable communication framework for 3D Wireless Network‐on‐Chip (WiNoC) systems by introducing dynamic, power‐aware routing and intelligent flow management techniques. Traditional routing approaches often suffer from high power consumption, congestion, and limited adaptability, which hinder the performance and energy efficiency of densely integrated, multi‐layer chip architectures. To overcome these limitations, this work proposes DynaQ‐NoC, an intelligent and scalable communication framework that leverages reinforcement learning to enable routers to make autonomous, context‐aware routing decisions based on local traffic, thermal, and power conditions. At its core, DynaQ‐NoC employs a Q‐learning‐based dynamic routing algorithm integrated with adaptive flow control mechanisms to balance network load, mitigate thermal hotspots in real‐time, and ensure energy‐efficient communication. Intelligent routing decisions are made dynamically to avoid congested or overheated regions, improving latency and reliability. Furthermore, DynaQ‐NoC introduces energy‐saving features such as sleep‐mode activation for idle links and efficient link utilization policies, which significantly contribute to reduced static energy consumption. The proposed system was implemented using Python and evaluated with a cycle‐accurate 3D WiNoC simulator using realistic traffic patterns. Results demonstrate that DynaQ‐NoC reduces power consumption by up to 30% compared to baseline methods and achieves an average power consumption of 82.3 mW. It also reduces latency by approximately 16% and maintains a routing decision accuracy of up to 92%. The system sustains a packet delivery ratio of over 95% under moderate traffic loads while ensuring high throughput scalability. These results validate DynaQ‐NoC's potential for enhancing system reliability, thermal stability, and energy efficiency in next‐generation multi‐core and 3D integrated circuits.