This paper presents a background calibration technique that employs ramp signals with different slopes to simultaneously correct timing skew and buffer-induced harmonic distortion in time-interleaved analog-to-digital converters (TI-ADCs). During harmonic distortion calibration, a slow ramp is applied to the input buffer, and nonlinear coefficients are extracted from its transfer characteristics. These coefficients enable accurate digital-domain compensation without degrading the quality of the input signal. For skew calibration, a steep ramp is introduced to detect timing mismatches, providing an input-independent solution that imposes no constraints on the input signal. Furthermore, it avoids periodic variations in input impedance and prevents the generation of additional spurious tones. A 2.5-GS/s 12-bit TI-ADC behavioral model combined with transistor-level front-end circuits is developed to validate the proposed methods. Simulation results show significant improvements in SFDR across the entire frequency range, with skew-induced spurs effectively removed and harmonic distortion greatly suppressed.
Yu et al. (Thu,) studied this question.