What question did this study set out to answer?

The aim is to design a CNN hardware architecture integrated with BIST for enhanced reliability and self-testing capabilities.

March 28, 2026Open Access

Design and Implementation of a CNN Core with Integrated Built-In Self-Test (BIST) Architecture on FPGA using Verilog HDL

Key Points

The aim is to design a CNN hardware architecture integrated with BIST for enhanced reliability and self-testing capabilities.
Developed a CNN core in Verilog HDL with integrated BIST features.
Utilized LFSR for pseudo-random test pattern generation.
Implemented on Xilinx Artix-7 FPGA using Vivado software.
Conducted resource usage and fault coverage analysis.
The design operates efficiently at 58 MHz with a total power consumption of 0.253 W.
Demonstrated scalable performance suitable for safety-critical embedded systems.
Achieved effective self-detection of faults without human intervention.

Abstract

Abstract: This paper introduces a single hardware architecture that combines the core of a Convolutional Neural Network (CNN) with a Built-In Self-Test (BIST) subsystem in Verilog HDL. The design uses a Linear Feedback Shift Register (LFSR) in favor of. Multiple Input pseudo-random generation of test pat- terns and generation of test patterns pseudo-random test pattern generation. Output response analysis Signature Register (MISR) compact 2-D convolution and ReLU activation is performed by the CNN for 4 x 4 input windows of 3 x 3 kernel with 12 bit signed fixed -. point arithmetic. The suggested single architecture can be used to support both inference and self-test modes, which provide self-detection of crashes without human intervention. Implemented on a. The design is extremely fast with Xilinx Artix- 7 FPGA with Vivado. low software overhead, 58 MHz and 0.253 W. total power consumption. The work suggested has shown an AI hardware design approach which is scalable and fault-tolerant enough. on safety critical embedded systems. Additionally, this work offers comprehensive resource usage, time-based analysis and fault coverage analysis done in order to bring out realistic implementation capability. Keywords: CNN, BIST, LFSR, MISR, Verilog HDL, Fault Detection, FPGA, Self-Test, Hardware Testing, Reliability. Title: Design and Implementation of a CNN Core with Integrated Built-In Self-Test (BIST) Architecture on FPGA using Verilog HDL Author: Shanti Swarup Dash, Shashank Kumar, Saksham Dubey International Journal of Electrical and Electronics Research ISSN 2348-6988 (online) Vol. 14, Issue 1, January 2026 - March 2026 Page No: 26-38 Research Publish Journals Website: www.researchpublish.com Published Date: 20-March-2026 DOI: https://doi.org/10.5281/zenodo.19132403 Paper Download link (Source) https://www.researchpublish.com/papers/design-and-implementation-of-a-cnn-core-with-integrated-built-in-self-test-bist-architecture-on-fpga-using-verilog-hdl

Design and Implementation of a CNN Core with Integrated Built-In Self-Test (BIST) Architecture on FPGA using Verilog HDL

Key Points

Abstract

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