Semiconductor Wafer Map Defect Classification Using Convolutional Neural Networks on Imbalanced Classes

This paper presents a deep learning-based approach for classifying defects on wafer maps, a critical task in semiconductor manufacturing. The proposed method utilizes convolutional neural networks (CNNs) to enhance defect detection accuracy while addressing class imbalance through data augmentation and oversampling techniques. The model is trained and evaluated using the WM-811K wafer defect map dataset, a widely used benchmark for defect classification. Experimental results demonstrate that the proposed approach significantly improves classification performance, particularly for underrepresented defect classes. Performance metrics, including precision, recall, F1 score, and area under the precision-recall curve (AUC), are used to assess the effectiveness of the model. Additionally, Gradient-weighted Class Activation Mapping (Grad-CAM) is employed to provide visual explanations of network decisions. The F1 scores for the defect classes “Center,” “Donut,” “Edge-Loc,” “Edge-Ring,” “Loc,” “Near-full,” “Random,” “Scratch,” and “None” are 0.93381, 0.88358, 0.84492, 0.97374, 0.72098, 0.89655, 0.89844, 0.62222, and 0.95259, respectively. In addition, the area under the curve (AUC) for these defect classes are 0.96996, 0.94735, 0.9166, 0.92802, 0.81741, 0.87061, 0.93121, 0.64507, and 0.9916, respectively. The results indicate that deep learning models can offer a reliable and scalable solution for defect classification, contributing to improved quality control and yield optimization in semiconductor manufacturing.