Key points are not available for this paper at this time.
We reveal the origin of disturbance issues in ferroelectric FETs (FeFETs) with a metal-gate interlayer (G. IL) -ferroelectric (FE) -channel interlayer (Ch. IL) -Si (MIFIS) stack. To achieve both low-voltage operation and disturbance immunity, we introduce a multi-functional TiO₂ layer, positioned between the G. IL and FE layer. TiO₂ multi-functional layer (MFL) serves two pivotal roles: (1) It forms a potential well that captures gate-injected charges, enhancing the memory window (MW). (2) It amplifies the domain size of the underlying FE layer, enabling steep polarization (P) switching behavior. Under the same operation voltage (V₎) which is below 15 V, MIFIS FeFET with TiO₂ improves the MW by 35 % compared to the device without TiO₂. Notably, the proposed device remains disturbance-free (Vₓ₇ 0\ V) even after 104 cycles of 9 V disturbance stress, whereas the TiO2- free counterpart experiences severe disturbance (Vₓ₇ 3. 5\ V) under the same conditions. We attribute this difference to the partial P properties of FE layers. Using a model framework which reflects the hysteresis sub-loop of FE, we clarify that partial P acts as the primary driver of disturbances, as it precedes charge trapping and accelerates charge injection from the gate. This study highlights the potential of MIFIS FeFET for future NVM applications by decoupling the trade-off between low-voltage operation and disturbance issues.
Kim et al. (Sat,) studied this question.