Chemistry of Si-SiO2 interface trap annealing

The kinetics and chemistry of Si-SiO2 interface trap annealing are examined in detail. Measurements of interface trap density Dit as a function of anneal time were performed with several process variables as parameters: oxide thickness, anneal ambient, temperature, bulk carrier type, metallization damage, and orientation. Experiments were carried out using rapid thermal processing and capacitance-voltage measurements of aluminum gate metal-oxide-semiconductor capacitors. Anneal temperature and crystal orientation have the strongest effect on the kinetics. 〈100〉 interfaces can be described by a power-law temporal variation; 〈111〉 kinetics are slightly more complicated. In both cases the experimentally observed anneal behavior is in conflict with the commonly used second-order surface recombination model. We propose a two-reaction model involving atomic hydrogen dimerization and hydrogen/interface trap reactions. This model sucessfully predicts anneal kinetics over a temperature range of 170–500 °C, representing a 106 dynamic range in anneal rates. The difference in anneal behavior between 〈111〉 and 〈100〉 interfaces is explained by postulating different trap anneal mechanisms for the Pb0 and Pb1 defect centers. This hypothesis is supported by trap production kinetics induced by extended anneals.