A decoupled access-execute architecture for reconfigurable accelerators

Mapping computational intensive applications on reconfigurable technology for acceleration requires two main implementation parts: (a) the data plane, i.e., efficient interconnected units that accelerate processing, and (b) the access-plane, i.e., efficient ways to access data and transfer them to/from the accelerator. Data plane construction is well understood and mature tools -such as High Level Synthesis (HLS)- that produce efficient reconfigurable architectures exist. The access plane, however, is more challenging: data fetching for big-data and high-performance computing applications is even more complex and time consuming than processing.