FPGA Implementation of ECG Denoising using Kaiser Window Technique

ECG aids in identifying heart diseases like coronary heart disease, arrhythmias, and heart attacks. Before making a diagnosis, the electrocardiogram (ECG) signal must be cleaned up from any artefacts that are typically present. The signal is distorted due to noises like powerline interference noise, baseline wander noise etc. To remove such noises an FIR filter has been implemented. Coefficients specific to noises have been used to design FIR filters specific to noises in ECG. While designing the filter the performance aspects of the filter have been focused upon. A kaiser window has been implemented for good balance between the noise reduction and the distortion of the ECG signal. The impulse response has a finite period in a finite impulse response filter (FIR). The multiplier block, adder block, and flip flop block are the core building blocks for the creation and application of the FIR filter. The multiplier, which is the adder's slowest block, has a significant impact on the FIR filter's performance. The use of the Booth Multiplier and carry select adder in the Finite Impulse Response Filter has been proposed. The filter and other filters have been compared for several parameters. The proposed filter is designed and implemented with Verilog and Xilinx 14.7 Vivado tools. There has been a reduction in both the area and the delay. Using this FIR filter with coefficients specific to the noises in ECG the filter for denoising ECG has been obtained. ECG signals have been taken from the MIT-BIH arrhythmia database.