Leakage-Aware FinFET-Based CMOS Design for Sub-Threshold Computing Applications

The rapid growth of energy-constrained applications such as Internet of Things (IoT), wearable electronics, and biomedical implants has intensified the need for ultra-low power circuit design methodologies. Subthreshold computing has emerged as a promising solution by operating transistors below the threshold voltage, significantly reducing dynamic power consumption. However, leakage currents become dominant in this regime, leading to degraded performance and reliability challenges. This paper presents a leakage-aware FinFET-based CMOS design framework optimized for sub-threshold computing applications. The proposed approach leverages the superior electrostatic control and reduced short-channel effects of FinFET technology to mitigate leakage currents while maintaining acceptable performance levels. A combination of adaptive threshold control, multi-fin optimization, and leakage reduction techniques such as gate work-function engineering and power gating is incorporated into the design. The proposed architecture is evaluated using standard benchmark circuits, demonstrating a significant reduction in leakage power by up to 35–45% compared to conventional planar CMOS designs, while maintaining competitive delay characteristics. Furthermore, the design shows improved energy efficiency and robustness against process variations, making it suitable for next-generation low-power embedded systems. The results highlight that FinFET-based CMOS circuits provide a viable pathway for achieving energy-efficient and reliable sub-threshold operation in modern nano-scale technologies.