The increasing computational demands of deep neural network inference drive the need for energy-efficient hardware accelerators that minimize data movement between memory and processing units. Compute-in-memory (CIM) architectures address this bottleneck by embedding computation directly within memory arrays, reducing the overhead of repeated weight transfers in conventional von Neumann systems. Conventional 6T SRAM-based digital CIM bitcells incur significant transistor overhead as arrays scale, motivating exploration of reduced-transistor bitcell alternatives. We propose a compact 4T+2T SRAM-based digital CIM bitcell implemented in 45 nm CMOS, combining a 4T SRAM storage cell with a 2T multiplier for bitwise multiply-and-accumulate (MAC) operations. The proposed design reduces transistor count from 8 to 6 compared to the 6T+2T reference, lowering parasitic capacitance and hardware overhead without compromising memory or computation functionality. Transient simulations confirm correct write, read, and CIM operations. The bitcell achieves a read delay of 26.91 ps, read power of 1.351 nW, and read energy of 0.005403 fJ—reductions of 98.7%, 86.5%, and 73.1% over the 6T+2T reference, respectively. For CIM operation, bitwise multiplication power decreases from 1.772 µW to 0.8014 µW and energy from 10.63 fJ to 4.808 fJ, representing a 54.8% reduction in both metrics, with only a marginal CIM delay increase of 3.13 ps. Monte Carlo analysis across 100 samples confirms robust write behavior under process variation, with write delay ranging from 55.02 to 69.59 ps and write energy from 0.05870 to 0.06557 fJ. Static noise margin analysis yields an SNM of 83.7 mV under nominal conditions, confirming stable data retention. These results demonstrate that the proposed 4T+2T bitcell offers strong transistor efficiency, energy savings, and computational correctness, making it a promising candidate for area-efficient digital CIM architectures targeting edge AI inference.
Hariprasad et al. (Sun,) studied this question.