In this paper, potential three-dimensional SOI CMOS VLSI circuit structures are laid out. Chip area, layout complexities, process costs, and impact on circuit performance are compared and discussed.

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Zhang et al. (Mon,) studied this question.

synapsesocial.com/papers/6a09760187ad1657d2515810 https://doi.org/https://doi.org/10.1109/soi.1999.819850

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Also Consider

Synapse has enriched 5 closely related papers on similar clinical questions. Consider them for comparative context:

1Homoepitaxial growth of CdTe on vicinal CdTe(100) surfaces: Reaction kinetics and mechanism1999 · 20 citations
2Three-dimensional stacked MOS transistors by localized silicon epitaxial overgrowth1990 · 44 citations
3MBE growth on vicinal GaAs(001) surfaces studied by scanning tunneling microscopy1992 · 39 citations
4Adsorption and reaction of diethylzinc on GaAs(100)1992 · 20 citations
5The reactivity of dimethylcadmium on GaAs(100) and CdTe(100)1997 · 3 citations