January 20, 2003

Architecture and performance of 3-dimensional SOI circuits

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Abstract

In this paper, potential three-dimensional SOI CMOS VLSI circuit structures are laid out. Chip area, layout complexities, process costs, and impact on circuit performance are compared and discussed.

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Cite This Study

Zhang et al. (Mon,) studied this question.

synapsesocial.com/papers/6a09760187ad1657d2515810 https://doi.org/https://doi.org/10.1109/soi.1999.819850

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