What question did this study set out to answer?

This research aims to enhance the power efficiency of large convolutional neural networks using resistive crossbar memory arrays.

July 23, 2018

Input-Splitting of Large Neural Networks for Power-Efficient Accelerator with Resistive Crossbar Memory Array

Puntos clave

This research aims to enhance the power efficiency of large convolutional neural networks using resistive crossbar memory arrays.
Developed a methodology for input-splitting of CNNs across multiple resistive crossbar arrays.
Retrained CNN models with proper initialization to substitute intermediate partial sums.
Conducted experimental comparisons of power consumption between the proposed and baseline designs.
ADC power consumption decreased by 32x in the proposed design compared to the baseline.
Total chip power consumption was reduced by a factor of 3 compared to the baseline design.

Resumen

Resistive Crossbar memory Arrays (RCA) have been gaining interest as a promising platform to implement Convolutional Neural Networks (CNN). One of the major challenges in RCA-based design is that the number of rows in an RCA is often smaller than the number of input neurons in a layer. Previous works used high-resolution Analog-to-Digital Converters (ADCs) to compute the partial weighted sum in each array and merged partial sums from multiple arrays outside the RCAs. However, such approach suffers from significant power consumption due to the need for high-resolution ADCs. In this paper, we propose a methodology to more efficiently construct a large CNN with multiple RCAs. By splitting the input feature map and retraining the CNN with proper initialization, we demonstrate that any CNN model can be represented with multiple arrays without using intermediate partial sums. The experimental results show that the ADC power of the proposed design is 32x smaller and the total chip power of the proposed design is 3x smaller than those of the baseline design.

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