A Mathematical Co-Design Framework for Synchronous Boost DC-DC Converters and PI Controllers Under Parasitic and Semiconductor Loss Effects

This paper proposes a mathematical co-design framework for synchronous Boost DC-DC converters and their PI voltage controllers. In contrast to the conventional sequential design approach, where the power stage is sized first and the controller is tuned afterward, the proposed method treats the converter and the controller as a single coupled design problem. A nonlinear averaged model of the synchronous boost converter operating in continuous conduction mode is considered, explicitly incorporating the inductor series resistance, the capacitor equivalent series resistance, and the on-state resistances of the active switches. In addition, a simplified but physically interpretable loss model is included in order to capture inductor copper loss, capacitor ESR loss, semiconductor conduction loss, and switching loss. Based on this formulation, the joint design of the power stage and the PI controller is cast as a constrained multi-objective optimization problem whose decision variables include the inductance, capacitance, switching frequency, and controller gains. The optimization criteria account for output-voltage ripple, settling time, total losses, and current stress, while practical constraints related to duty cycle, current limits, ripple bounds, and closed-loop feasibility are enforced. The proposed framework makes it possible to compute Pareto-efficient designs and to reveal trade-offs that remain hidden under classical decoupled design procedures. Numerical case studies are structured to compare the proposed co-design strategy with a conventional sequential-design baseline. An optional technology-aware extension is also considered, allowing the influence of different semiconductor classes, such as Si, SiC, and GaN, to be assessed through technology-dependent loss and switching-frequency assumptions. The results indicate that the proposed framework provides a mathematically grounded and practically useful basis for integrated converter–controller synthesis in nonideal power electronic systems.