Complementary Logic Driven by Dielectrophoretic Assembly of 2D Semiconductors

Abstract 2D semiconductors have emerged as promising channel materials for complementary logic circuits in future electronics. Efforts to scale them beyond a few‐device‐level demonstrations toward practical circuit fabrication have primarily relied on chemical vapor deposition or solution‐based exfoliation of bulk crystals into 2D nanosheets. While the latter offers a facile and cost‐effective approach for producing 2D semiconductors, scalable fabrication and integration of complementary doping schemes to produce complex integrated circuits has been challenging. Here, a scalable, parallel fabrication strategy is developed to realize 2D semiconductor‐based complementary logic gates through electric‐field‐driven deterministic assembly of nanosheet dispersions. Arrays of n ‐type and p ‐type semiconducting channels are formed by selectively assembling electrochemically exfoliated MoS 2 and WSe 2 nanosheets between source and drain electrodes using alternating current dielectrophoresis (AC‐DEP), followed by solution‐based chemical treatment to passivate chalcogen vacancies. Under optimal AC‐DEP processing conditions, the MoS 2 and WSe 2 field‐effect transistors (FETs) exhibit average field‐effect mobilities of 4.3 and 3.0 cm 2 V −1 s −1 , respectively, and average on/off current ratios exceeding 10 4 . The capability of the approach to precisely position n ‐channel and p ‐channel FETs enables scalable and parallel fabrication of diverse complementary logic gates—such as NOT, NAND, and NOR—and static random access memory.