VLSI Synthesis for Low-Power Clocking in Synchronous Designs

In the field of information theory, the significance of low-power techniques cannot be overstated. Among these, clock gating stands out as a potent method to mitigate power dissipation in synchronous designs. The landscape has been further shaped by VLSI innovations, which, in their initial stages, necessitated substantial equipment, incurred high power consumption, and exhibited occasional unreliability. This paper explores the evolution from these challenges to a paradigm where advancements in VLSI technology have resulted in smaller, more affordable, reliable, and power-efficient systems. Focusing on the Arithmetic Logical Unit (ALU) design, our study presents a comparative analysis of power consumption across various existing clock gating techniques. Introducing an innovative signal clock gating method, we address contemporary challenges with an accessible mechanism, enhancing immunity. Our proposed Gated Clock Generation design, employing a tri-state connection and logic gate, demonstrates superior power savings, even when applied to the target module. This approach optimizes power efficiency in digital design while proving particularly effective in reducing dynamic power within logic circuits. Implementing an improved gate-based clock gating technique in ALU design, our results show a noteworthy reduction in clock delay (71% to 78%), a 23% improvement in area, and a substantial 66.67% enhancement in power efficiency. Notably, this clock gating scheme surpasses alternative methods in terms of area requirements. The experiments, exclusively conducted on ALU design, utilized 130 nm standard logic libraries for implementation. The design architecture was meticulously crafted using Verilog HDL, and simulations were executed with ModelSim-Altera 10.0c (Quartus II 11.1) Starter Version.