Enhancing Computational Speed and Accuracy in Circuit Design Calculations using ANN

Abstract The efficiency of Latch design and optimization plays a crucial role in shaping the overall performance of digital circuits, impacting power consumption and timing within emerging system-on-chip (SOC) archi-tectures. This paper introduces a methodology for modeling, designing, and optimizing 65nm D-Latch positive-edge-triggered Latch. Leveraging an Arti-ficial neural network (ANN)-based optimization ap-proach, an accurate model is first generated for vari-ous performance metrics using training data acquired from transistor-level models, which surpass tradi-tional methods by over 100 times in speed. Sub-sequently, these precise ANN-based models are em-ployed to optimize design objectives such as setup time, and propagation delay (Data to Output). The utilization of these swift and precise models markedly expedites the design process and yields significantly optimized outcomes. Furthermore, given the ANN’s capacity as a universal approximator capable of cap-turing any nonlinear input-output relationship, the proposed method is adaptable to optimizing circuits for diverse performance metrics, even in the absence of analytical formulas. Additionally, the automation of circuit design through the proposed method sim-plifies the tasks of circuit designers.