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Three-dimensional integrated circuits can significantly mitigate the challenges posed by shrinking feature sizes and enable heterogeneous integration. This paper focuses on the 3D floorplanning problem. We formulate it as a multi-objective optimization issue and employ multi-objective simulated annealing to simultaneously optimize area, wirelength and number of vias. During the optimization process, neighboring solutions are explored in the design space through inter-layer or intra-layer perturbations, and decision criteria for the exploration process are formulated based on the dominance relationship of solutions. Test results on the GSRC benchmark demonstrate that our approach delivers superior performance in optimizing area and wirelength. Compared to 2D floorplanning, our method reduces the area by approximately 49% and the wirelength by 21%. Compared to other similar 3D floorplanning methods, we raise the success rate in satisfying the fixed-outline constraint to 100% and improve the wirelength by 3%. The multi-objective simulated annealing method proposed in this paper can effectively address the 3D floorplanning problem.
Jiang et al. (Sat,) studied this question.