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Abstract As the resolution and conversion speed of Time-to-Digital Conversion (TDC) chips continue to improve, the bit error rate also increases, leading to a decrease in the linearity of TDC and seriously affecting measurement accuracy. This paper presents a high linearity, low power consumption, and wide dynamic range TDC that has been achieved based on the SMIC 180 nm V3E BCD process. Compared with previous research methods, the proposed phase arbiter structure can eliminate sampling errors and improve the linearity of TDC. The preprocessing circuit can eliminate fixed errors caused by Start and Stop signal transmission delays. Post-simulation results show that the TDC has high linearity, with ranges of DNL and INL being − 0.76LSB < DNL < 0.89LSB, and − 0.59LSB < INL < 0.73LSB, respectively. The highest resolution is 150 ps, dynamic range is 2.5 ms, and the power consumption is 1.73 mW. The overall system architecture of TDC is very simple, and it can be applied to dToF LIDAR to measure photon flight time, capable of measuring a range of up to a kilometer, with an accuracy of 2.25 centimeters, high linearity, and without any post-processing or time calibration.
Chen et al. (Wed,) studied this question.
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