Fault Injection Tool for FPGA Reliability Testing: A Novel Method and Discovery of LUT-Specific Logical Redundancies

FPGAs are well suited for prototyping complex digital systems for industrial and research purposes, as well as for the practical application of artificial intelligence (AI) methods in industrial autonomous control, automotives and space. FPGAs serve as platforms for inferring based on AI algorithms. In recent years, an increase in FPGA system applications with respect to advanced computing functions for physical and chemical research in space has been observed. Research on the reliability of applications operating in the above-mentioned areas exposed to radiation is of particular importance. Testing applications implemented on FPGAs requires the development of new methods that differ significantly from those intended for Application-Specific Integrated Circuits (ASICs). The FPGA logic is realized by SRAM-Based Look-Up Tables (LUTs). SRAM is relatively susceptible to single-event upsets (SEUs) generated by cosmic radiation. The existing fault injection (FI) tools do not model the faults generated by SEUs in SRAM-based FPGAs precisely enough. New FI tools are crucial for evaluating newly developed FPGA-specific tests. Thus, we developed a new tool that uses an accurate SEU model in LUTs. This new tool is written in Perl, and its tasks are to inject faults into the structural VHDL description and to control the CADENCE simulator. The novelty of this solution is that the tool models SEUs by modifying the logical functions generated by the LUTs. Furthermore, in this way, stuck-at faults at the LUT inputs and outputs can also be modeled. This method involves modifying the “INIT” parameters in the structural VHDL. Our tool was evaluated using several test programs, and a high fault coverage (FC) of 94.76% was achieved. This tool can be used to examine any LUT-based FPGA technology regardless of its implementation age. Moreover, during our research, a new mechanism of generating so-called logical redundancies caused by the injection of single faults in LUTs was discovered. This is a side effect of FI in LUTs, which makes it impossible to achieve 100% fault coverage of applications implemented on FPGAs. The mechanism of this phenomenon does not occur when injecting traditional stuck-at faults.