A low phase noise Multiply-Delay Locked Loop (MDLL) with uniform distribution multiple output clock phases is proposed in this paper. An auto-configured time amplifier (ACTA) with high gain is embedded in the phase frequency detector to reduce the static phase offset (SPO) and output phase noise. Additionally, a multiplexer (MUX) with dynamic load matching is adopted to achieve more precise clock injection. Test results indicate that the MDLL implemented by the TSMC 0.18μm 1.8V standard CMOS process can successfully boost the frequency of the output clock to 500MHz with an input reference frequency of 25MHz, where the phase separation of the 4 clocks is locked around (45±2.1)°. The phase noise at a 1MHz frequency offset is -117.3dBc/Hz, the integrated RMS value of random jitter is about 2.28ps, the core area is approximately 0.089 mm 2 , and the core power is 5.886mW, suitable for TDC application.
Yang et al. (Thu,) studied this question.