A CMOS VLSI Design for Low-Power High-Sensitivity Sensor Interface Circuits Using Bayesian Sampling Plan–Based Quality Control

This paper presents a FinFET-based CMOS VLSI design for low-power, high-sensitivity sensor interface circuits integrated with a Bayesian sampling plan–based quality control framework to enhance manufacturing reliability and performance consistency. The proposed sensor interface employs a 16-nm FinFET CMOS technology, enabling reduced leakage current and improved electrostatic control compared to planar CMOS designs. To address process variations and yield uncertainty at advanced technology nodes, a Bayesian acceptance sampling plan is incorporated to statistically monitor and control critical performance parameters during fabrication. The designed sensor interface achieves an input-referred sensitivity of 1.92 μ V/√Hz, a dynamic range of 92.6 dB, and a signal-to-noise ratio (SNR) of 78.4 dB, while operating at a supply voltage of 0.8 V. Post-layout simulations show a total power consumption of 8.3 μ W, representing a 31.7% reduction compared to conventional CMOS-based sensor interfaces. The FinFET architecture further reduces leakage power by 42.5%, improving low-power operation for battery-driven and IoT sensor nodes. The Bayesian sampling plan evaluates wafer-level performance using prior and posterior distributions of key metrics such as gain, offset, and power consumption. The proposed quality control method reduces false rejection probability by 23.8% and improves yield estimation accuracy by 28.4% compared to classical single-sampling plans. Overall, the combined FinFET VLSI design and Bayesian quality control framework enhances robustness, energy efficiency, and production yield, making the proposed sensor interface highly suitable for precision sensing applications in biomedical, environmental monitoring, and cyber-physical systems.