ABSTRACT Series resonant voltage‐controlled oscillator (SR‐VCO) provides an effective solution for achieving ultralow noise due to their larger voltage swing. To further reduce the phase noise, a class‐F SR‐VCO architecture is proposed in this paper. By introducing a zero at the third harmonic of the resonant frequency, a drain current comprising fundamental and third harmonic components is generated, resulting in a pseudo‐square wave current waveform. This significantly reduces the effective pulse sensitivity function (ISF) of the VCO, leading to an improved noise figure. The paper details the design methodology for the class‐F SR‐VCO and validates it at 2.71‐ to 2.93‐GHz frequency band. Implemented with SMIC180‐nanometer standard CMOS, the VCO demonstrates an average phase noise of 139.9 dBc/Hz and a figure of merit (FOM) of 186.7 dB at 1‐MHz offset. The designed class‐F SR‐VCO consumes 119.5‐mA current from a 1.2‐V power supply.
Tang et al. (Wed,) studied this question.