Radix-2, radix-4, and radix-2k are some variations of the Fast Fourier Transform (FFT) algorithm, which is used to calculate the Discrete Fourier Transform (DFT) of a sequence. Among these, the radix-2k algorithm is particularly noteworthy because of its low-power requirements, versatility, and straightforward control logic. To provide a simplified butterfly unit with low memory requirements, the suggested radix-2k architecture uses a Multiple Delay Commutator (MDC). Data shifting along the delay line is controlled by an input scheduling algorithm, which also helps to reduce power usage. To support high-speed applications, this work proposes a radix-2² FFT design with a Vedic multiplier. The design is implemented on a Xilinx Virtex-5 FPGA board for 8-point, 16-point, 512-point, and 1024-point FFTs. In particular, the 1024- point Radix-2² FFT architecture uses 121 registers, 11,629 LUTs, and 5,515 slices to achieve a delay of 42.102 ns. Integration of a Vedic multiplier within the butterfly unit resulted in improved operational performance and reduction in area. The performance analysis in terms of energy and latency was also compared with different adders.
NANCHARAIAH et al. (Wed,) studied this question.