As DRAM technology nodes move into the sub-10 nm regime, capacitor scaling is increasingly constrained by both footprint loss and a hard physical thickness limit for the entire electrode–dielectric–electrode stack. Under these conditions, the long-standing TiN/ZrO2/TiN platform approaches a point where further equivalent oxide thickness (EOT) reduction would require ultrathin dielectrics with unacceptable leakage. Rutile TiO2 is attractive as a post-ZrO2 dielectric because its intrinsically high permittivity can, in principle, deliver sub-0.3 nm EOT at practical thicknesses while retaining process simplicity as a binary oxide and leveraging the broad atomic layer deposition (ALD) precursor availability. The crucial barrier is manufacturable rutile stabilization within the DRAM thermal budget, especially on industry-standard TiN, together with leakage suppression in TiO2 with a small band gap and intrinsic n-type nature. This Spotlight highlights integration-driven pathways for low-temperature rutile stabilization, spanning templated growth on rutile-compatible conductive oxides and nontemplated strategies on TiN and then discusses leakage control through electrode choice, interlayer band engineering, and defect and dopant management. We close by outlining the key process and materials milestones required to translate rutile TiO2 from a promising concept into a scalable DRAM dielectric platform.
Jeon et al. (Mon,) studied this question.