This paper presents a MoS2-based Gate-All-Around Ferroelectric Negative Capacitance FET (GFNCFET) with h-BN dielectric and HZO ferroelectric gate for ultra-low power electronics. TCAD simulations demonstrate minimum subthreshold swing of 81.6 mV/dec approaching the thermal limit of conventional MOSFET operation, with voltage amplification factor of 1.02 confirming negative capacitance operation. The device exhibits 12-decade current modulation (10−12 to 10−2 A) with on/off ratio exceeding 1010. Ferroelectric characterization reveals remnant polarization of 0.30 C/m2 with characteristic S-shaped Landau hysteresis. The gate-all-around architecture with atomically thin MoS2 achieves DIBL of 28 mV/V. Results validate GFNCFET as a promising architecture for energy-efficient post-CMOS electronics.
Christiane et al. (Tue,) studied this question.