Cost‐Effective Winner‐Take‐All Approach for Comparing Multi‐Output Neural Networks

This work focuses on designing a winner‐take‐all (WTA) algorithm using digital circuits, rather than the more commonly used analog circuits. In this context, neurons are represented as digital bits, similar to those in convolutional neural networks (CNNs) and weightless neural networks (WNNs). The proposed WTA circuit compares the most significant bits (MSBs) of all neurons (or discriminators) in parallel. The results of this initial comparison are then used to evaluate the second MSBs, where a parallel comparison is performed. This process continues iteratively for each subsequent bit until the least significant bits (LSBs) are analyzed. By removing less significant neurons early in the process, the number of signals that switch activity in subsequent comparisons is decreased, thereby reducing overall dynamic power. The WTA circuit consists of an array of OR–AND configurations that employ low‐cost CMOS logic gates and operate without a clock or any form of synchronization. This design inherits the advantages of scalability and configurability: adding a new neuron requires only inserting a new row of cells, while increasing the size of the neurons can be accomplished by adding new columns of cells. The design characteristics rely on two factors: the number of neurons ( K ) and the size of each neuron ( N bits). Neuron size plays a crucial role in determining the critical path delay.