Operational Geometry of Noise in Superconducting Processors

Accurate modeling of noise is a central challenge for scaling superconducting quantum hardware. Standardapproaches typically assume stationary, memoryless and gate-local noise. On current processors with morethan one hundred qubits, these approximations break down: we observe short-term drift, history dependence,device-wide fluctuations and non-monotonic idle behavior.We introduce an operational measure of two-qubit noise, the information distance di j(t) = −lnFi j(t), defineddirectly from GHZ2 fidelities. This quantity is empirical and time dependent. Crucially, it does not followphysical distance on the hardware graph: adjacent qubits can have large di j, while multi-hop connections canhave smaller di j. The resulting “noise geometry” is induced by information flow rather than physical layout.Using more than 50 000 circuits across three IBM heavy-hex processors (Marrakesh, Fez and Torino), weobserve usage-dependent changes of 0.002–0.02 in di j, minute-scale relaxation, slower device-wide drift andnon-monotonic idle-time distinguishability. These local variations accumulate along multi-qubit paths. Onibm marrakesh, a trained seven-qubit path outperforms a baseline GHZ7 circuit in all 20 interleaved trials,with a mean fidelity gain of 1.6×10−2and reduced variance.We summarize these observations with a minimal dynamical model in which information distances evolve under usage, relaxation, local fluctuations and a global drift process. The results indicate that noise on present-daysuperconducting processors is time dependent, history dependent and structured in a way that is not captured bystatic gate-local models, and that operational information distance provides a practical geometry for describingthis structure.