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Integration of the hard disk controller (HDC) today has taken on an extensive amount of functionality. From the host interface, error correction code, disk sequencer, microprocessor(s), servo control logic, buffer controller, to the embedded memory, the HDC has become a true system on a chip. Depending on the product, embedded DRAM is used as buffering for data between the host and media and possibly for storing controller firmware. By bringing all these blocks into one chip, pin counts can be reduced and higher data flow speeds can be obtained by decreasing the interconnect delays. However, the challenge for designers is in test and verification of the design during development and production.
Jeppesen et al. (Wed,) studied this question.