A 6.5 GHz 130 nm single-ended dynamic ALU and instruction-scheduler loop

32b Han-Carlson ALU and 8-entry /spl times/ 2-ALU instruction scheduler loop for 6.5 GHz single-cycle integer execution at 1.2 V and 25/spl deg/C uses dual-Vt CMOS technology. A single-ended, leakage-tolerant dynamic scheme enables up to 9-wide ORs with 23% critical path speed improvement, 40% active leakage power reduction compared to Koggie-Stone implementation, dense layout occupying 44, 100 /spl mu/m/sup 2/, and performance scalable to 8 GHz at 1.5 V, 25/spl deg/C.