Key points are not available for this paper at this time.
NASA's Wide-Field Infrared Survey Telescope (WFIRST) project has developed the ACADIA ASIC, a next generation detector control and acquisition system-on-a-chip. The purpose of this ASIC is to address the stringent requirements of operating a cryogenic detector in a spacecraft environment. Key performance criteria are low analog noise and low power consumption at temperatures between 150K and 180K while supporting the full dynamic range of the sensor. The ASIC is primarily intended to operate the Teledyne H4RG for WFIRST, but has been designed with considerable flexibility to provide compatibility with a large selection of other detectors. Up to 40 analog sensor outputs can processed in parallel, where each signal is amplified and conditioned by a low-noise pre-amplifier with programmable gain and bandwidth, and then digitized by a 16-bit successive approximation analog-to-digital converter (ADC). The ASIC includes 24 analog output channels that can be configured as programmable voltage or current sources, and are used to generate biases and references to the detector. A simple-to-program sequencer provides timing control for the detector and the ASIC internal circuits, with the option of using an embedded microprocessor for more elaborate readout schemes. This paper presents an overview of the ACADIA ASIC design with detailed descriptions of its analog, mixedsignal, and digital circuit blocks. First prototypes of the ACADIA ASIC have been fabricated, and preliminary test results of functionality and performance have been measured. We discuss the test environment and the obtained results, and conclude by describing the next steps for the project. The ACADIA ASIC is intended to operate the Teledyne H4RG infrared hybrid detector (current baseline for the WFIRST Wide-Field Instrument), but has been designed with considerable flexibility to provide compatibility with a large selection of other detectors. Each analog sensor output is amplified and conditioned by a low-noise pre-amplifier with programmable gain and bandwidth, and then digitized by a 16-bit successive approximation analog-to-digital converter (ADC). Up to 40 signals can be processed in parallel. Some basic math functions like summing, averaging, threshold comparison, and digital gain are available per channel. In addition, the ASIC includes 24 analog output channels that can be configured as programmable voltage or current sources, and are used to provide biases and references to the detector. Overall timing control is provided by a flexible but simple-to-program sequencer, with the option of microprocessor control for more elaborate readout schemes. Further digital capabilities include Direct Memory Access (DMA) engine, timers, Serial Peripheral Interface (SPI), and science data formatting for transmission. All circuitry has been protected against single event effects from ionizing radiation. We will discuss the status of the development effort, with focus on the performance requirements, general design features, and available test results. Over the course of the development, several test chips have been built that have already demonstrated significant improvements in analog performance over prior solutions, and have shown compliance with key WFIRST requirements for both cryogenic and room temperature operation. Prototypes of the full 40-channel ACADIA ASIC have been fabricated and are currently being tested. In addition to the chip itself, the packaging approach, test environment, and control electronics with computer acquisition will be presented.
Siskind et al. (Tue,) studied this question.