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This paper presents efficient VLSI architectures for 2-D FIR filters exploiting Four-Fold Rotational Symmetry (FRS) and Octagonal Symmetry (OS) in the coefficient matrices, combined with parallel processing and a dual-port Distributed Arithmetic (DA)–based computation approach. By incorporating symmetry properties, the number of unique filter coefficients is significantly reduced, resulting in substantial savings in multipliers and overall arithmetic complexity. The remaining multiplications are implemented using a modified dual-port LUT-based DA, which minimizes memory size, power consumption, and critical path delay compared to conventional DA techniques. Parallel processing with a block size L is employed to enhance throughput by a factor of L , while maintaining efficient memory usage. Two symmetry-specific filter architectures, one based on four-fold rotational symmetry and the other on octagonal symmetry, are designed, analyzed, and optimized using the proposed DA scheme. Each architecture is implemented in Verilog HDL and synthesized on an FPGA using Xilinx tools to obtain hardware utilization, timing, and power metrics. Further, ASIC synthesis using Cadence Genus in 45-nm CMOS technology is performed to evaluate area, delay, and power, followed by physical design and layout generation using Innovus. The ASIC synthesis results for the proposed architectures in 45nm CMOS technology show that the OS architecture achieves a maximum reduction of 97.42% in Area Delay Product (ADP) and 89.41% in Power Delay Product (PDP)compared to the state-of-the-art designs. Moreover, the FRS architecture achieves a balanced optimization in ADP reduction by 89.15% and a reduction in PDP by 29.43%. Statistical validation for images proves that these huge hardware reductions are achieved while maintaining a quality retention rate of 98% in SSIM and PSNR values of 0.932 and 29.52 dB, respectively, demonstrating their high utility for real-time vision and image dehazing applications.
Odugu et al. (Mon,) studied this question.