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This study presents a novel topology of charge‐transferring zero‐current‐switching (CT‐ZCS) inverter to improve the efficiency. Its operating principle, optimal zero‐current‐switching (ZCS) frequency and design guidelines are elucidated in detail. A reduced‐order modelling method of time‐charge discretisation, which treats a set of two separate ZCS as one combined switch cell, is put forward and the topology can be simplified to dual‐buck half‐bridge inverter (DBHBI) topology. Since the DBHBI‐derived CT‐ZCS inverter permits higher comparison frequency of hysteresis control than traditional hard‐switching inverters, the three‐level relay control with high‐frequency pulse modulation is recommended. Compared with two‐level and three‐level hysteresis control, the proposed control can achieve effective output harmonic reduction, decreasing from 2.335 to 1.66%, and minimise the size of inverter under the same output condition. In addition, a current controller is designed to optimise the system and enhance its anti‐disturbance performance. Finally, the experiment on a 35‐V 2‐A prototype verifies the validity of the proposed method.
Liu et al. (2016) studied this question.